Design a Capacitor From Bare Geometry

Use C = K × ε₀ × A / d: multiply the dielectric constant by the vacuum permittivity (8.854 × 10⁻¹² F/m) and the overlapping plate area in square metres, then divide by the plate separation in metres. For example, two 25 mm² plates on opposite sides of 1.6 mm FR-4 give 4.2 × 8.854×10⁻¹² × 25×10⁻⁶ ÷ 1.6×10⁻³ ≈ 0.58 pF. The calculator above performs the conversion from mm², cm², m², sq in or sq ft, and from µm, mm, cm, m, mil or inches, so only the numbers themselves need to be entered.

ε₀ is the vacuum permittivity: 8.8541878128 × 10⁻¹² farads per metre. It is the proportionality constant that converts geometry (area divided by gap) into capacitance when the gap is empty space. Every material multiplies it by its relative permittivity K. The number is not arbitrary — it falls out of the speed of light and the magnetic constant (c² = 1/ε₀µ₀) — which is why no amount of geometry cleverness escapes it: vacuum capacitor designs all inherit the same tiny base value.

Barium titanate, by a wide margin: K ≈ 1200 for Class 2 formulations, with some compositions reaching into the thousands. It is the ceramic inside common MLCC decoupling capacitors. The practical trade-offs are voltage and precision — high-K ceramics lose capacitance under DC bias, drift with temperature, and carry loose tolerances (Z-band in extreme cases). For stable values, lower-K materials win: C0G/NP0 ceramics (K ≈ 20–100), film (≈ 2–3) and mica (≈ 7) hold their value across voltage, temperature and time.

Because high K is not the only requirement. Water is a polar molecule: it conducts impurities readily, electrolyses under DC bias, freezes at 0 °C, boils at 100 °C, and its permittivity collapses above a few GHz. A water-dielectric capacitor leaks, corrodes its plates and changes value with every degree. The lesson generalises: the K column of the table is a starting point, and usable dielectrics must also hold off voltage, stay stable and refuse to conduct — which is why ceramics, polymers and oxides dominate.

Chiefly in the fringing regime. The formula assumes the field between the plates is uniform and simply ends at the plate edges; in reality it bulges outward, adding edge capacitance the formula never counts. When the plate dimensions are at least 50× the gap, the error is negligible. Below about 10× the gap, the error grows past 10% and the calculator's result becomes a floor rather than a value. The formula also assumes the dielectric fills the gap completely — an air bubble or partial fill creates a series combination of two capacitors, not one clean value.

You do not have to — enter area in mm², cm², m², square inches or square feet, and separation in µm, mm, cm, m, mils or inches, picking from the dropdown beside each field. For reference: 1 sq in = 645.16 mm², 1 mil = 25.4 µm, and a US 0603 pad pair overlaps roughly 0.5 mm². Once the value is computed, the result is quoted in auto-picked units from pF upward; if you need it in a specific unit, the capacitance converter page translates pF, nF, µF, mF and F in one step.

Yes — and the stacking rule depends on how you wire it. N identical plate capacitors wired in parallel add directly (N × C), which is exactly what a multi-plate air variable capacitor does by interleaving plates: every adjacent pair is one parallel contribution. Wired in series, N equal capacitors give C/N with N-fold voltage rating — useful for high-voltage probes, at the cost of value. The series & parallel calculator handles both combinations for up to 12 arbitrary values, including mixed units.

More than intuition suggests, less than a component does. Two default pads across a 1.6 mm FR-4 core: ~0.6 pF. Wide traces over a ground plane in a 4-layer stack (gap 0.2 mm): several pF per centimetre of run. An interleaved interdigitated comb structure can reach tens of pF in a few square millimetres. That range — fractions of a pF to tens of pF — is exactly why board-level parasitics matter for RF and sensing and are ignorable for digital decoupling. Compute your own geometry above before trusting a layout rule of thumb.